An FPGA-Based Convolutional Neural Network Coprocessor

In this paper, an FPGA-based convolutional neural network coprocessor is proposed. The has a 1D computation unit PE in row stationary (RS) streaming mode and 3D chain pulsating array structure. can flexibly control the number of openings according to output channels layer. we design storage system with multilevel cache, global cache uses multiple broadcasts distribute data local caches propose image segmentation method that compatible hardware architecture. proposed implements pooling layers VGG16 model, which activation value, weight bias value are quantized using 16-bit fixed-point quantization, peak computational performance 316.0 GOP/s average 62.54 at clock frequency 200 MHz power consumption about 9.25 W.